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always @ ({signal1, signal2, etc}) triggers syntax error, unexpected '{' #745

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veripoolbot opened this issue Apr 21, 2014 · 3 comments
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always @ ({signal1, signal2, etc}) triggers syntax error, unexpected '{' #745

veripoolbot opened this issue Apr 21, 2014 · 3 comments
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area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed

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Author Name: Igor Lesik
Original Redmine Issue: 745 from https://www.veripool.org
Original Date: 2014-04-21
Original Assignee: Wilson Snyder (@wsnyder)

I am trying to compile big project where some designers concatenate signals inside "always" sensitivity list. All other Verilog compilers we have in house do not have any problems with this syntax, so I suspect it is Verilator bug.

I would appreciate if someone confirms that it is a bug and give ETA for fixing it. If there are no resources then I might try to fix it myself; and in this case I will appreciate any pointers to the (parser ?) code as I am absolutely not familiar with Verilator code.

Thanks,
Igor
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Original Redmine Comment
Author Name: Igor Lesik
Original Date: 2014-04-21T21:36:41Z

forgot to mention that version is 3.856

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-21T23:40:36Z

One-liner. Fixed in git towards 3.857.

Note verilator has very limited syntax in always as it is cycle based.

Also I suspect you'll gain performance with other simulators by using "or" instead of an event expression.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:08:51Z

In 3.860.

@veripoolbot veripoolbot added area: parser Issue involves SystemVerilog parsing resolution: fixed Closed; fixed labels Dec 22, 2019
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