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Strings are limited in width to 64 bits #746

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veripoolbot opened this issue Apr 21, 2014 · 3 comments
Closed

Strings are limited in width to 64 bits #746

veripoolbot opened this issue Apr 21, 2014 · 3 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Glen Gibb
Original Redmine Issue: 746 from https://www.veripool.org
Original Date: 2014-04-21
Original Assignee: Wilson Snyder (@wsnyder)

Verilator generates an error whenever I try to assign a string longer than 64 bits to a string variable. For example, trying to compile the attached file produces the following errors on the longStr string assignment line:

%Warning-WIDTH: t/t_string_print.v:8: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's CONST '72'h313233343536373839' generates 72 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-21T23:28:45Z

Verilator only supports strings in a few limited cases, and not currently compares. I'm in the middle of a ripup of V3Width, after this is released this should be easier to fix.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-11-28T20:02:07Z

Fixed in git towards 3.867.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-20T21:52:26Z

In 3.868.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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