Verilog::Preproc doe not sustitute module type in instance. #751
Comments
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Original Redmine Comment Obviously the preprocessor doesn't care about modules or not, so it's extremely unlikely to be a bug in Verilog-Perl. Please check your script carefully; you didn't provide #�.pl; perhaps it is not actually defining anything since you must be overloading something to have it print "ticDefine". |
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Original Redmine Comment Found the problem. My bad. |
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Original Redmine Comment Great! |
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Author Name: Tim Jordan
Original Redmine Issue: 751 from https://www.veripool.org
Original Date: 2014-04-29
Here's in:
`define LOWER lower
`define IF_UPB_BUS_REV if_upb_bus_v2c0
module #�
(
output logic o,
input logic i
);
ifdef UPPERUPPER ( o, i );`endif
endmodule:#�
and here's out:
[jordant@helium #�] % ./#�.pl #�.sv
ticDefine : 'LOWER' 'lower' ''
ticDefine : 'IF_UPB_BUS_REV' 'if_upb_bus_v2c0' ''
`line 1 "#�.sv" 1
module #�
(
output logic o,
input logic i
);
endmodule:#�
`line 21 "#�.sv" 2
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