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Verilog AUTO_TEMPLATE : matching multiple strings #753

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veripoolbot opened this issue Apr 29, 2014 · 1 comment
Closed

Verilog AUTO_TEMPLATE : matching multiple strings #753

veripoolbot opened this issue Apr 29, 2014 · 1 comment
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Author Name: Sandip Das
Original Redmine Issue: 753 from https://www.veripool.org
Original Date: 2014-04-29
Original Assignee: Wilson Snyder (@wsnyder)


Hi,
I am trying to achieve the following connection with the AUTO_TEMPLATE below.
the following ports of module na_xyz should be connected to signals as follows

     PORT                    SIGNAL
 ------------------------------------
  abc_A*USER              agentA_A*USER
  abc_W*USER              agentA_W*USER
  abc_ARCACHE             agentA_ARCACHE
  abc_AWCACHE             agentA_AWCACHE
  abc_ARQOS               agentA_ARQOS
  abc_AWQOS               agentA_AWQOS

so i came up with the following AUTO_TEMPLATE but it does not work.
any idea how to make it work ?

/* ns_xyz AUTO_TEMPLATE (
.abc_([AW].*USER|A[RW]CACHE|A[RW]QOS) (agentA_\1[]),
);
*/

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-07T00:21:08Z


The template you provided works perfectly for me, maybe there is something else wrong.

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