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Issue #754

Verilator bug with shift, expression width and signedness

Added by Clifford Wolf over 3 years ago. Updated over 3 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
WrongRuntimeResult
% Done:

0%


Description

Verilator fb4928b seems to have troubles with the following expressions. It seems to correctly interpret -2'sd1 as the value 3, but then has problems identifying the correct bit width for the expression and sign extends it even though the result of << should be unsigned.

module issue_003(a, y);
  input signed [3:0] a;
  output [4:0] y;
  assign y = a << -2'sd1;
endmodule

Crosscheck: Vivado 2013.4, XST 14.7, Xsim 2013.4 and Modelsim 10.1d implement this correctly.

Self-contained test case:
http://svn.clifford.at/handicraft/2014/verilatortest/test007.v
http://svn.clifford.at/handicraft/2014/verilatortest/test007.cc
http://svn.clifford.at/handicraft/2014/verilatortest/test007.sh

Verilog testbench for comparison:
http://svn.clifford.at/handicraft/2014/verilatortest/test007_tb.v

History

#1 Updated by Clifford Wolf over 3 years ago

Sorry: I copied the wrong GIT sha1. This is for GIT version adb39ce.

#2 Updated by Wilson Snyder over 3 years ago

  • Category set to WrongRuntimeResult
  • Status changed from New to Closed
  • Assignee set to Wilson Snyder

The result of the << is not unsigned. It's signed as a is signed and only the LHS matters. 'a' needed sign extension instead of the bug which was to extend the << result.

VCS gets this wrong too - a sign that you're deep into a dark corner ;)

Fixed in git; this was broken by yesterday's commit; the released version gets it correct, so closing.

#3 Updated by Clifford Wolf over 3 years ago

Wilson Snyder wrote:

The result of the << is not unsigned. It's signed as a is signed and only the LHS matters.

You are of course right. I just checked with the standard document and Yosys source code. I implemented it correctly in Yosys but somehow remembered it wrong..

Thanks for the fix. I'll rerun my tests and see what I can find next.

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