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Verilator bug with shift, expression width and signedness #754

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veripoolbot opened this issue Apr 30, 2014 · 3 comments
Closed

Verilator bug with shift, expression width and signedness #754

veripoolbot opened this issue Apr 30, 2014 · 3 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 754 from https://www.veripool.org
Original Date: 2014-04-30
Original Assignee: Wilson Snyder (@wsnyder)

Verilator fb4928b seems to have troubles with the following expressions. It seems to correctly interpret -2'sd1 as the value 3, but then has problems identifying the correct bit width for the expression and sign extends it even though the result of << should be unsigned.

  input signed [3:0] a;
  output [4:0] y;
  assign y = a << -2'sd1;
endmodule

Crosscheck: Vivado 2013.4, XST 14.7, Xsim 2013.4 and Modelsim 10.1d implement this correctly.

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test007.v

http://svn.clifford.at/handicraft/2014/verilatortest/test007.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test007.sh

Verilog testbench for comparison:

http://svn.clifford.at/handicraft/2014/verilatortest/test007_tb.v
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Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-04-30T17:08:37Z

Sorry: I copied the wrong GIT sha1. This is for GIT version adb39ce.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-01T02:47:11Z

The result of the << is not unsigned. It's signed as a is signed and only the LHS matters. 'a' needed sign extension instead of the bug which was to extend the << result.

VCS gets this wrong too - a sign that you're deep into a dark corner ;)

Fixed in git; this was broken by yesterday's commit; the released version gets it correct, so closing.

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Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-05-01T08:43:07Z

Wilson Snyder wrote:

The result of the << is not unsigned. It's signed as a is signed and only the LHS matters.

You are of course right. I just checked with the standard document and Yosys source code. I implemented it correctly in Yosys but somehow remembered it wrong..

Thanks for the fix. I'll rerun my tests and see what I can find next.

@veripoolbot veripoolbot added area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed labels Dec 22, 2019
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed
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