Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 762 from https://www.veripool.org
Original Date: 2014-05-10
Original Assignee: Wilson Snyder (@wsnyder)

Consider the following test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test011.v

http://svn.clifford.at/handicraft/2014/verilatortest/test011.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test011.sh

http://svn.clifford.at/handicraft/2014/verilatortest/test011_tb.v

Most of the code is just there to confuse verilator. The important bit is this line:

Besides other things this connects y[37:34] directly to the input a0.

The test bench sets all input bits to zero, evaluates and prints y[37:34]. Then it sets all input bits to one, re-evaluates and prints y[37:34] again.

One would expect the output 0000 for the first iteration and 1111 for the second iteration. But the output is 0000 in both cases.

If the first iteration is skipped and the inputs are directly set to all-one then the output is 1111 as expected.

The circuit has no memory elements and is acyclic: http://i.imgur.com/K88J0ds.png