Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-24T17:20:30Z

Hint: Try changing two bits.

Spoiler: It's a reduction XOR so if you change one bit you flip between % 0 or % 1.

Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-05-24T17:34:27Z

Wilson Snyder wrote:

Spoiler: It's a reduction XOR so if you change one bit you flip between % 0 or % 1.

argwl. thanks. I'm coding verilog for over 10 years now and every now and then I see a prefix ^ and think it is a bitwise inverse (~).. ;)

Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-05-24T17:47:36Z

jfyi: I've now changed the text of the bug report in the vloghammer tracker to the following:

Verilator f705f9b prints %Error: rtl.v:4: Unsupported: 4-state numbers in this context
for the following input:

 :::Verilog
 module issue_052(y);
   output [3:0] y;
   assign y = ((0/0) ? 1 : 2) % 0;
 endmodule

The strange part is this: The statements assign y = (0/0) % 0; and
assign y = (0/0) ? 1 : 2; are both accepted by Verilator.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-10T02:27:24Z

Had to think how I wanted to handle this - which is a division by zero but detected later than usual, after Xs should have been removed.

Fixed in git towards 3.861.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:58:42Z

In 3.862.