Strange Verilator "Unsupported" Error
Verilator f705f9b prints "%Error: rtl.v:4: Unsupported: 4-state numbers in this context" for the following input:
module issue_052(y); output [3:0] y; assign y = ((0/0) ? 1 : 2) % ^8'b10101010; endmodule
The strange part is this: If I change any bit in 8'b10101010 then Verilator accepts the code.
#3 Updated by Clifford Wolf almost 5 years ago
jfyi: I've now changed the text of the bug report in the vloghammer tracker to the following:
Verilator f705f9b prints `%Error: rtl.v:4: Unsupported: 4-state numbers in this context` for the following input:
:::Verilog module issue_052(y); output [3:0] y; assign y = ((0/0) ? 1 : 2) % 0; endmodule
The strange part is this: The statements `assign y = (0/0) % 0;` and `assign y = (0/0) ? 1 : 2;` are both accepted by Verilator.
#4 Updated by Wilson Snyder almost 5 years ago
- Category set to TranslationError
- Status changed from New to Resolved
- Assignee set to Wilson Snyder
Had to think how I wanted to handle this - which is a division by zero but detected later than usual, after Xs should have been removed.
Fixed in git towards 3.861.
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