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Strange Verilator "Unsupported" Error #775
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Original Redmine Comment Hint: Try changing two bits. Spoiler: It's a reduction XOR so if you change one bit you flip between % 0 or % 1. |
Original Redmine Comment Wilson Snyder wrote:
argwl. thanks. I'm coding verilog for over 10 years now and every now and then I see a prefix ^ and think it is a bitwise inverse (~).. ;) |
Original Redmine Comment jfyi: I've now changed the text of the bug report in the vloghammer tracker to the following: Verilator f705f9b prints
The strange part is this: The statements |
Original Redmine Comment Had to think how I wanted to handle this - which is a division by zero but detected later than usual, after Xs should have been removed. Fixed in git towards 3.861. |
Original Redmine Comment In 3.862. |
Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 775 from https://www.veripool.org
Original Date: 2014-05-24
Original Assignee: Wilson Snyder (@wsnyder)
Verilator f705f9b prints "%Error: rtl.v:4: Unsupported: 4-state numbers in this context"
for the following input:
The strange part is this: If I change any bit in 8'b10101010 then Verilator accepts the code.
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