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Virtual Interface modport issue #778
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Original Redmine Comment The data_type's yVIRTUAL rules are missing the ['.' modport_identifier]. Unfortunately three attempts of adding this all are making the grammar explode (because '.' can also be used to reference a member of an interface, and the grammar can't know the difference). Let me give it more thought. |
Original Redmine Comment Figured it out. Fixed in git towards 3.404. |
Original Redmine Comment In 3.404. |
Original Redmine Comment Wilson, Thanks,
|
Original Redmine Comment Classes fixed in git towards 3.409. |
Author Name: Jon Nall
Original Redmine Issue: 778 from https://www.veripool.org
Original Date: 2014-05-30
Original Assignee: Wilson Snyder (@wsnyder)
The following code (taken generally from IEEE 1800-2009 spec Section 25) results in an error due to using a modport in the virtual statement. I believe this code should parse without error.
Verilog-Perl generates: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final
@interface foo;
wire a, b, c, d;
modport master (input a, b, output c, d);
modport slave (output a, b, input c, d);
endinterface : foo
virtual foo.master bar;
@
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