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Support covergroup #784

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veripoolbot opened this issue Jun 10, 2014 · 3 comments
Open

Support covergroup #784

veripoolbot opened this issue Jun 10, 2014 · 3 comments
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area: coverage Issue involves coverage generation effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800

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@veripoolbot
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Author Name: Alex Solomatnikov
Original Redmine Issue: 784 from https://www.veripool.org
Original Date: 2014-06-10


Example RTL:

     covergroup cg_forward_path_control @(posedge clk);
        rd_state:   coverpoint {rd_cnt_not_zero, rd_deq} {
           illegal_bins illegal = { 2'b01 };
        }

        f_state:    coverpoint {f_uop_v, f_issue} {
           illegal_bins illegal = { 2'b01 };
        }

        rt_state: coverpoint {rt_cnt_not_zero, rt_fsm_v, rt_to_issue_v, rt_issue} {
           wildcard illegal_bins illegal = { 4'b??01 };
        }

        ry_state:  coverpoint {ry_cnt_not_zero, ry_to_issue_v, ry_issue} {
           wildcard illegal_bins illegal = { 3'b?01 };
        }

        state_cross: cross rd_state, f_state, rt_state, ry_state {
           wildcard illegal_bins ill1 = (binsof(rd_state) intersect { 2'b1? })   && ( (binsof(f_state)  intersect { 2'b?1 })   ||
                                                                                      (binsof(rt_state) intersect { 4'b???1 }) ||
                                                                                      (binsof(ry_state) intersect { 3'b??1 }) );
           wildcard illegal_bins ill2 = (binsof(f_state)  intersect { 2'b?1 })   && ( (binsof(rt_state) intersect { 4'b???1 }) ||
                                                                                      (binsof(ry_state) intersect { 3'b??1 }) );
           wildcard illegal_bins ill3 = (binsof(rt_state) intersect { 4'b???1 }) &&   (binsof(ry_state) intersect { 3'b??1 });
        }

        b2d_control: coverpoint {b2d_needed_pulse, b2d_v, b2d_v_d1, b2d_v_wait, b2d_out_en} {
           wildcard illegal_bins ill1 = { 7'b???11?? };
           wildcard illegal_bins ill2 = { 7'b?????01 };
        }
        option.per_instance = 1;
     endgroup // cg_forward_path_control

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-10T02:00:23Z


This be great to have a patch for, as I don't think there is anyone working on this.

BTW another related project I would like to see is moving the SystemPerl coverage scripts into the verilator kit itself.

@veripoolbot veripoolbot added area: coverage Issue involves coverage generation effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
@kaddkaka
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Is there any progress on this?

It would also be helpful to just ignore covergroups instead of triggering an error when finding them.

@wsnyder
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wsnyder commented May 31, 2020

No, coverage is a major project expected to start next year.

Perhaps you'd be able to contribute some tests and a patch to ignore them? IThe full parsing for cover groups is commented out in verilog.y (as Verilog-Perl could parse them) so this shouldn't be too bad,

@wsnyder wsnyder changed the title Support for SystemVerilog coverage Support for SystemVerilog covergroup Sep 16, 2023
@wsnyder wsnyder changed the title Support for SystemVerilog covergroup Support covergroup Sep 16, 2023
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Labels
area: coverage Issue involves coverage generation effort: weeks Expect this issue to require weeks or more of invested effort to resolve type: feature-IEEE Request to add new feature, described in IEEE 1800
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