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Support for SystemVerilog assertions #785
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Original Redmine Comment Verilator supports concurrent SVA assertions. e.g. always @ (posedge clk) begin It could probably support "assert property" where the syntax is very limited to the PSL subset. I'll take this as the request of this bug. $fell etc are a pain and unlikely to be any time soon. |
Original Redmine Comment I'll have a fix for this shortly. Still NOT supported will be:
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Original Redmine Comment UPDATE: there IS a fundamental difficulty supporting unclocked combinational concurrent asserts -- they're not allowed by the verilog spec. We will support concurrent asserts that omit the sensitivity list, and thus depend on a prior declaration of a default clock. That will work for 'assert property' like it already does for 'cover property'. |
Original Redmine Comment Here's the fix. commit c8cf2af (HEAD -> master, origin/master, origin/HEAD)
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Original Redmine Comment Fixed in git towards 3.922 |
Author Name: Alex Solomatnikov
Original Redmine Issue: 785 from https://www.veripool.org
Original Assignee: John Coiner (@jcoiner)
Change log says:
However, verilator errors out even for simple single cycle assertion:
Error:
Slightly more complex assertion (single cycle after reset):
Produces 2 errors:
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