typedef logic [$clog2(32)-1:0]   id_t;
typedef logic [$clog2(26+1)-1:0] way_cnt_t;

module test_ver_bug( input logic clk,
                      input id_t  id );

    way_cnt_t completed_cnt   [32-1:0][2-1:0];
    way_cnt_t completed_cnt_dp        [2-1:0];

    assign completed_cnt_dp = completed_cnt[id];

    always_ff @(posedge clk) begin
       completed_cnt[id] <= completed_cnt_dp + 1;
    end

endmodule // test_ver_bug

verilator -sv --sp --top-module test_ver_bug test_ver_bug.v
%Error: Internal Error: test_ver_bug.v:13: ../V3Slice.cpp:277: ArraySel dtyping failed when resolving slice
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /tools/verilator/verilator-3.860/bin/verilator_bin -sv --sp --top-module test_ver_bug test_ver_bug.v

    logic [4-1:0] uop_state_dp[2-1:0];

    e_flop #($bits(r_rc_state)) u_r_rc_state_ff( .o(r_rc_state), 
                                                 .i((r_enq &&
                                                     r_would_be_empty &&
                                                     (uop_state_dp != `STATE_COMP0)) ? rc_state :
                                                                                       rc_state[r_head_id_comb]),
                                                 .en((r_enq && r_would_be_empty) ||
                                                     (!(r_enq && r_would_be_empty) && (r_deq && r_cnt_not_zero && !r_cnt_is_one)) ),
                                                 .* );