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incorrect RTL under assert() causes verilator to produce incorrect C++ #796

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veripoolbot opened this issue Jun 27, 2014 · 1 comment
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resolution: duplicate Closed; issue or pull request already exists

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Author Name: Alex Solomatnikov
Original Redmine Issue: 796 from https://www.veripool.org
Original Date: 2014-06-27


RTL:

  input logic [40-1:0] way_mask,
  ...
  logic [40-1:0] addr[32-1:0][2-1:0];
  ...
  always_ff @(posedge clk) begin
     if( match ) begin
        assert( (addr[id] & way_mask) == 0 ); // way is not set yet
        ...
     end
  end

C++ error:

env_top.sp:33732:12: error: invalid operands of types 'uint64_t [2] {aka long unsigned int [2]}' and 'uint64_t {aka long unsigned int}' to binary 'operator&'

Probably related to #�.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-28T00:15:32Z


Same basic problem as #�.

@veripoolbot veripoolbot added the resolution: duplicate Closed; issue or pull request already exists label Dec 22, 2019
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Labels
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