New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Port width issue - v3.201 #80
Comments
Original Redmine Comment Please note that Wilson has already provided a solution for me: From: Wilson Snyder wsnyder@wsnyder.org
Please try the following patch and let me know if you have other issues. -Wilson
|
Original Redmine Comment Thanks for bugging this. I fixed this and just pushed version 3.202 now, since this was a fairly serious problem. |
Author Name: Derek Johnstone
Original Redmine Issue: 80 from https://www.veripool.org
Original Date: 2009-05-01
Original Assignee: Wilson Snyder (@wsnyder)
I am having some issues with port widths for ports defined using Verilog 2001 syntax. Basically if the port has a defined width (i.e. is not a single bit) then all is well, but if it is a single bit port defined after another bus port, the single bit port seems to take the width of the previous bus port. e.g.
module TEST
(
output [11:0] DACL_DATA,
output ADCCLK
);
endmodule
using $port->net->dump on ADCCLK you can see that the port is defined with a width of 12. e.g.
Net:ADCCLK I DeclT:port NetT: DataT:[11:0] Array: 11:0
Net:DACL_DATA I DeclT:port NetT: DataT:[11:0] Array: 11:0
However if you declare ADCCLK first then ADCCLK has the correct width defined. e.g.
Net:ADCCLK I DeclT:port NetT: DataT: Array:
Net:DACL_DATA I DeclT:port NetT: DataT:[11:0] Array: 11:0
Re-ordering ports connections isn't really a solution so I was wondering if there was a way round this issue? Can you specify which Verilog syntax is being used (e.g. Verilog 2001) before loading the module?
Many thanks for your help.
The text was updated successfully, but these errors were encountered: