bug with bit-swap inside a large signal (more than 64 bits) #800
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: fixed
Closed; fixed
Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 800 from https://www.veripool.org
Original Date: 2014-07-03
Original Assignee: Wilson Snyder (@wsnyder)
Verilator generates incorrect code for the following:
@tmp@ and @TMPP@ will be different in the simulation.
A test case can be pulled here https://github.com/jiexu/verilator/tree/bitsSwap
The text was updated successfully, but these errors were encountered: