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bug with bit-swap inside a large signal (more than 64 bits) #800

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veripoolbot opened this issue Jul 3, 2014 · 3 comments
Closed

bug with bit-swap inside a large signal (more than 64 bits) #800

veripoolbot opened this issue Jul 3, 2014 · 3 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 800 from https://www.veripool.org
Original Date: 2014-07-03
Original Assignee: Wilson Snyder (@wsnyder)


Verilator generates incorrect code for the following:


// ---------------------------------------------------------------------------
// combinational blocks / continuous assignament
// ---------------------------------------------------------------------------
always_comb begin: b_test
     logic [127:0] tmpp;
     logic [127:0] tmp;
     tmp  = 0;
     tmpp = 0;

     tmp[63:0]  = val;
     tmpp[63:0] = val;

     tmpp[63:0] = {tmp[0+:32], tmp[32+:32]};
     tmp[63:0]  = {tmp[0+:32], tmp[32+:32]};
end


@tmp@ and @TMPP@ will be different in the simulation.

A test case can be pulled here https://github.com/jiexu/verilator/tree/bitsSwap

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-07-04T13:18:18Z


One of the optimization steps got confused by the same var on LHS and RHS. "-Ox" could be used to disable this and get the correct result.

Fixed in git towards 3.863.

@veripoolbot
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Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2014-07-04T13:23:14Z


thanks.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-21T13:10:33Z


In 3.864.

@veripoolbot veripoolbot added area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed labels Dec 22, 2019
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Labels
area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed
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