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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-07-09T12:06:41Z
There is support for all of system verilog so '0 should work fine. I run your example "vhier --cells quote_zero.sv" and it works, so I'm not seeing what is wrong. Does this work for you? Are you sure you're running the latest version (although this should have been working for years)?
Original Redmine Comment
Author Name: Am A
Original Date: 2014-07-10T00:29:35Z
My apologies, you're absolutely correct. I had an issue with an old version of the Verilog::Language library being referenced unexpectedly. This works correctly on the newest version.
Author Name: Am A
Original Redmine Issue: 801 from https://www.veripool.org
Original Date: 2014-07-09
The Verilog-Perl tool processes the attached file with the following errors:
I tried this out in QuestaSim, and it's building there.
Thanks!
Here's a copy of the file for reference, if it's helpful:
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