%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:25: Signal declaration outside of module definition
Exiting due to errors

`timescale 1ns / 1ps 
interface my_if
(
     input logic i_clock,
     input logic i_reset
);

     logic i_signal, o_signal;

     assign i_signal = o_signal;

     modport first_port (
         input
             i_clock,
             i_reset,
             i_signal
     );

     modport second_port (
         input
             i_clock,
             i_reset,
         output
             o_signal
     );

endinterface: my_if

`timescale 1ns / 1ps
module interface_test
(
     input logic i_clock,
     input logic i_reset,

     my_if.first_port m_first,
     my_if.second_port m_second
);
     
     another_module
     u_am
     (
         .i_clock(i_clock),
         .i_reset(i_reset),

         .m_first(m_first)
     );

endmodule

`timescale 1ns / 1ps
module another_module
(
     input logic i_clock,
     input logic i_reset,

     my_if.first_port m_first
);

endmodule