Author Name: Jonathon Donaldson
Original Redmine Issue: 804 from https://www.veripool.org
Original Date: 2014-07-20
Original Assignee: Wilson Snyder (@wsnyder)

I have been having great success with Verilator. However, I'm running into one very minor issue right now. I can think of a work-around but I want to know the best way to do this - if there is one.

I have a system verilog package that I created solely for the purpose of accessing certain functions/parameters that I use within my design. I did this so that I don't have to have a bunch of /verilator public/ comments cluttering up my design. In summary what I did was this (not checked for syntax correctness but you get the idea):

package My_Design_Imported_Package_1;
localparam MY_PARAM1 = 1;
endpackage

package My_Design_Imported_Package_2;
localparam MY_PARAM2 = 2;
endpackage

package My_Verilator_NonImported_Package;
import My_Design_Imported_Package_1::;
import My_Design_Imported_Package_2::;

localparam VERILATOR_PARAM1 /verilator public/ = MY_PARAM1;
localparam VERILATOR_PARAM2 /verilator public/ = MY_PARAM2;

endpackage

The package "My_Verilator_NonImported_Package" is not imported anywhere within my design. I was hoping I could use it just to get access to some parameters without having to actually import it anywhere.

However, what I found was that unless I actually 'import' the package somewhere in the design verilator optimizes the package away.

Is there any way to accomplish what I'm trying to do? I can think of a work-around - which is to create a wrapping veratilor-only testbench module which wraps around my real design and then import the verilator-only package into that module. But I was hoping to avoid that if possible...