Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

systemverilog power operator should support real numbers #809

Closed
veripoolbot opened this issue Aug 21, 2014 · 5 comments
Closed

systemverilog power operator should support real numbers #809

veripoolbot opened this issue Aug 21, 2014 · 5 comments
Assignees
@wsnyder
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor

Author Name: Jonathon Donaldson
Original Redmine Issue: 809 from https://www.veripool.org
Original Date: 2014-08-21
Original Assignee: Wilson Snyder (@wsnyder)

Is there any particular reason why verilator doesn't allow 'real' typed numbers when using the power (i.e. '**') operator? The SystemVerilog standard says that real numbers should be allowed. It's actually done that way so that it matches the behavior of the C library's pow() function.

I have some code I'm trying to compile that looks like this:

localparam real C_VID_CLK_FREQ_HZ = 25_000_000;

// Frame Rate
localparam real C_VID_FRAME_RATE_HZ_REAL = (HSYNC_CNT_MAX * VSYNC_CNT_MAX * (C_VID_CLK_FREQ_HZ**-1))**-1;

And verilator is giving me this error:
@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-08-22T01:32:19Z

Simply something that hasn't been fixed yet. Might you provide a patch?

First, make a test in test_regress, and see it fail, then make it pass... Then there's already a AstPowD operator (power on doubles), so in V3Width.c change the AstPow function to convert that node into an AstPowD. You'll see similar code for AstAdd becoming AstAddD.

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2014-08-23T01:00:50Z

Providing a regression test is certainly trivial. But I've got no clue how an AST works or even what it is for that matter (except what wikipedia tells me :)). Of course, I'm willing to look at the code and see if something clicks. And maybe the AstAddD example will help...but looking at the code right now it looks like complete greek to me. Haha. I haven't the slightest idea how the code base even works. So I'm coming at this from 0, but again, I'll give it a shot........

Just don't hold your breathe. :)

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-21T12:25:51Z

Making a release so thought I'd throw this in for you.

Fixed in git towards 3.863.

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-09-21T13:10:11Z

In 3.864.

@veripoolbot
Copy link
Contributor Author

Original Redmine Comment
Author Name: Jonathon Donaldson
Original Date: 2014-09-23T06:33:59Z

Way cool! Thanks a lot! Now I can look at the diff and see what changes you made and maybe learn enough to create some patches in the future...

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@wsnyder wsnyder

Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@wsnyder @veripoolbot