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Wrong alignment on 'virtual' keyword #817

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veripoolbot opened this issue Sep 5, 2014 · 4 comments
Closed

Wrong alignment on 'virtual' keyword #817

veripoolbot opened this issue Sep 5, 2014 · 4 comments
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Author Name: Enzo Chi
Original Redmine Issue: 817 from https://www.veripool.org
Original Date: 2014-09-05

I have 1 virtual interface and 1 virtual function declaration in my code are aligned as below:

class base_test extends uvm_test;
    `uvm_component_utils(base_test)

    typedef virtual my_if my_vif_t;

    virtual         function void start_of_simulation_phase(uvm_phase phase);
       super.start_of_simulation_phase(phase);
    endfunction : start_of_simulation_phase
endclass : base_test

You can see the 'function' keyword is aligned with my interface name. What I expect is:


class base_test extends uvm_test;
    `uvm_component_utils(base_test)

    typedef virtual my_if my_vif_t;

    virtual function void start_of_simulation_phase(uvm_phase phase);
       super.start_of_simulation_phase(phase);
    endfunction : start_of_simulation_phase
endclass : base_test
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Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2015-06-22T17:14:48Z

I also see this issue.

To add more information, this happens only if @verilog-auto-lineup@ variable is set to a non-nil option, like @'declarations@.

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Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2015-06-22T19:13:11Z

I have updated my fork with a fix for this: kaushalmodi@d2ce9f3

Please let me know if it works for you. (The fix will not correct the prior incorrectly indented code.)

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Original Redmine Comment
Author Name: Kaushal Modi
Original Date: 2015-07-20T13:18:00Z

The above fix for @virtual@ keyword misalignment has worked great for me till date.

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Original Redmine Comment
Author Name: Alex Reed
Original Date: 2015-07-21T02:30:16Z

Merged into 5939690

Thanks for the patch!

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