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How can I make AUTOLOGIC to combine multiple signal into a 2-d array input?
In the example, I instantiated module "a" twice with a output logic [3:0] y. I want to combine these two output into a 2d array logic [1:0][3:0] to module "b".
The AUTOLOGIC works fine breaking up 2d array output to multiple instance as shown in the example for signal x; However, it doesn't work when I try to do the opposite.
module a
();
/*AUTOLOGIC*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [1:0] [3:0] x; // X is correct but not y
logic [1:0] y; // How can I make y to be logic [1:0][3:0]?
// End of automatics
/* b AUTO_TEMPLATE
(// Outputs
.y (y[@]),
// Inputs
.x (x[@]));
);
*/
b i0_b
(/*AUTOINST*/
// Outputs
.y (y[0]), // Templated
// Inputs
.x (x[0])); // Templated
b i1_b
(/*AUTOINST*/
// Outputs
.y (y[1]), // Templated
// Inputs
.x (x[1])); // Templated
c i_c
(/*AUTOINST*/
// Outputs
.x (x/*[1:0][3:0]*/),
// Inputs
.y (y/*[1:0][3:0]*/));
endmodule
module b
(input logic [3:0] x,
output logic [3:0] y
);
endmodule
module c
(output logic [1:0] [3:0] x,
input logic [1:0] [3:0] y
);
endmodule
The text was updated successfully, but these errors were encountered:
Author Name: Victor Lau
Original Redmine Message: 1437 from https://www.veripool.org
How can I make AUTOLOGIC to combine multiple signal into a 2-d array input?
In the example, I instantiated module "a" twice with a output logic [3:0] y. I want to combine these two output into a 2d array logic [1:0][3:0] to module "b".
The AUTOLOGIC works fine breaking up 2d array output to multiple instance as shown in the example for signal x; However, it doesn't work when I try to do the opposite.
The text was updated successfully, but these errors were encountered: