Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 820 from https://www.veripool.org
Original Date: 2014-09-14
Original Assignee: Wilson Snyder (@wsnyder)

Hi, verilator crashed while compiling the next example:

git clone git@github.com:jeras/rv32_1stage_sv.git
cd rv32_1stage_sv
git checkout verilator_crash_01
./run_verilator.sh

The project is a RISC-V CPU (Verilog code generated from Chisel source), with a memory and a top file integrating the two. The C++ code is only providing clock and reset.

Regards,
Iztok Jeras