Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 823 from https://www.veripool.org
Original Date: 2014-09-23
Original Assignee: Wilson Snyder (@wsnyder)

This should return y=4'b100x for a=1, but verilator returns y=0 instead
(the MSB should be '1', obviously we don't care about the 'x' in the LSB that
is the result of the (by one bit) out-of-bounds part select):

 module issue_057(a, y);
   input [2:0] a;
   output [3:0] y;
   localparam [5:15] p = 51681708;
   assign y = p[15 + a -: 5];
 endmodule

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test020.v

http://svn.clifford.at/handicraft/2014/verilatortest/test020_tb.v

http://svn.clifford.at/handicraft/2014/verilatortest/test020.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test020.sh

This is with git e8edbad (verilator_3_864).