Author Name: Adam Krolnik
Original Redmine Issue: 847 from https://www.veripool.org
Original Date: 2014-11-13
Original Assignee: Wilson Snyder (@wsnyder)

In a filelist, handling the line +define+A+B does not match NC or VCS.
Both NC and VCS expand this line to be equivalent to +define+A +define+B, while Verilog-Perl
inteprets it as +define+A=B

L% cat b.lst
+define+A+B
b.v

L% cat b.v
module b;
reg [63:0] B; initial B = "B";
reg [63:0] C; initial C = "C";
ifdef C initial $display("C is %s", C );
endif ifdef B
initial $display("B was correctly found defined.");
else initial $display("B was not defined from +define+A+B. A was defined as %0s.", A);
`endif
endmodule

Both NC and VCS report:
B was correctly found defined.

Running vppprec (-f b.lst) I get:
...
initial $display("B was not defined from +define+A+B. A was defined as %0s.", B);

One suggested change to Verilog/Getopt.pm, line 130 (I don't understand the vcs_style logic.)
< elsif (($param =~ /^+define+([^+=])+=$/ # This is not correct + != =
< || $param =~ /^+define+(.?)()$/) && $self->{vcs_style}) {
< $self->define($1,$2,undef,1);
< }

NC/VCS also accept +define+A+B+C (equivalent to +define+A +define+B ...)

strings (A, A=B) can be combined with + to set multiple options. e.g. A+B=4+C+D=2

A

A=B

elsif ($param =~ /^+define+(.)$/) #Tokenize next
{
foreach my $tok (split("\+", $1))
{
my ($a, $b) = $tok =~ m/^([^=])=?(.*)$/;
$self->define($a,$b,undef,1);
}
}