genvar i;
generate for (i=0; i<4; i++) begin : gen_block
test_sub test_sub_x (
  .clk          (clk        ),
  .rst_n        (rst_n      ),
                             
  .data_in      (data_mid   ),
  .data_out     (data_out[i*2+:2]),
                             
  .data_valid   (data_valid),
  .data_enable  (data_enable_1[i])
);
end
endgenerate

generates the following output:
  Module test                                 test
        input clk
        output data_enable
        input data_in
        output data_out
        input data_valid
        input rst_n
       Cell test_sub_x
        .clk(clk)
        .data_enable(data_enable_1[i])
        .data_in(data_mid)
        .data_out(data_out[i*2+:2])
        .data_valid(data_valid)
        .rst_n(rst_n)
     Module test_sub                           test.test_sub_x
          input clk
          output data_enable
          input data_in
          output data_out
          input data_valid
          input rst_n
         Cell test_sub_sub_0
          .inny(rst_n)
          .outy(rst_n_buf)
       Module test_sub_sub                     test.test_sub_x.test_sub_sub_0
            input inny
            output outy
       Cell u_test_sub
        .clk(clk)
        .data_enable(data_enable_0)
        .data_in(data_in)
        .data_out(data_mid)
        .data_valid(data_valid)
        .rst_n(rst_n)