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trace-structs with pins_bv causes compiler errors #858

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veripoolbot opened this issue Dec 9, 2014 · 5 comments
Closed

trace-structs with pins_bv causes compiler errors #858

veripoolbot opened this issue Dec 9, 2014 · 5 comments
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resolution: fixed Closed; fixed

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Author Name: Eivind Liland
Original Redmine Issue: 858 from https://www.veripool.org
Original Date: 2014-12-09

Compilation fails when compiling the attached file as follows:

$ verilator --sc --trace --trace-structs --pins-bv 2 test_module.sv 
$ cd obj_dir && make -f Vtest_module.mk
/usr/bin/perl /usr/local/verilator/bin/verilator_includer Vtest_module.cpp Vtest_module___024unit.cpp > Vtest_module__ALLcls.cpp
g++  -I. -MMD -I/usr/local/verilator/include -I/usr/local/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=1 -DVM_COVERAGE=0       -pthread -I/usr/local/systemc/include  -c -o Vtest_module__ALLcls.o Vtest_module__ALLcls.cpp
/usr/bin/perl /usr/local/verilator/bin/verilator_includer Vtest_module__Trace.cpp Vtest_module__Syms.cpp Vtest_module__Trace__Slow.cpp > Vtest_module__ALLsup.cpp
g++  -I. -MMD -I/usr/local/verilator/include -I/usr/local/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=1 -DVM_COVERAGE=0       -pthread -I/usr/local/systemc/include  -c -o Vtest_module__ALLsup.o Vtest_module__ALLsup.cpp
In file included from Vtest_module__ALLsup.cpp:2:0:
Vtest_module__Trace.cpp: In static member function ‘static void Vtest_module::traceChgThis__3(Vtest_module__Syms*, VerilatedVcd*, uint32_t)’:
Vtest_module__Trace.cpp:56:55: error: invalid cast from type ‘sc_core::sc_in<sc_dt::sc_bv<2> >’ to type ‘IData {aka unsigned int}’
  vcdp->chgBit  (c+3,((1U & ((IData)(vlTOPp->test_input) 
                                                        ^
Vtest_module__Trace.cpp:58:54: error: invalid cast from type ‘sc_core::sc_in<sc_dt::sc_bv<2> >’ to type ‘IData {aka unsigned int}’
  vcdp->chgBit  (c+4,((1U & (IData)(vlTOPp->test_input))));
                                                       ^
In file included from Vtest_module__ALLsup.cpp:4:0:
Vtest_module__Trace__Slow.cpp: In static member function ‘static void Vtest_module::traceFullThis__1(Vtest_module__Syms*, VerilatedVcd*, uint32_t)’:
Vtest_module__Trace__Slow.cpp:76:56: error: invalid cast from type ‘sc_core::sc_in<sc_dt::sc_bv<2> >’ to type ‘IData {aka unsigned int}’
  vcdp->fullBit  (c+3,((1U & ((IData)(vlTOPp->test_input) 
                                                         ^
Vtest_module__Trace__Slow.cpp:78:55: error: invalid cast from type ‘sc_core::sc_in<sc_dt::sc_bv<2> >’ to type ‘IData {aka unsigned int}’
  vcdp->fullBit  (c+4,((1U & (IData)(vlTOPp->test_input))));
                                                        ^
make: *** [Vtest_module__ALLsup.o] Error 1
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-11T03:06:00Z

This works fine for me. Are you using the most recent version or git (see what verilator --version prints out.) If so, what version of SystemC?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-11T03:07:43Z

Woops, sorry, missed the --pins-bv. Will work on it.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-11T03:35:57Z

Fixed in git towards 3.867.

Tracing SystemC is a mess; Verilator already converts the signals to internal format and traces the signals in that internal format. E.g. there's a trace of "foo.test_input" (the sc signal) and "foo.v.test_input" (the converted signal), both will always show the same values. I disabled the former to fix this.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-20T21:52:49Z

In 3.868.

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Original Redmine Comment
Author Name: Eivind Liland
Original Date: 2015-01-12T10:23:11Z

tested here as well, works!

@veripoolbot veripoolbot added the resolution: fixed Closed; fixed label Dec 22, 2019
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