Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2015-01-12T04:08:03Z

anybody can help?

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-12T13:02:15Z

  .bus1\(.*\) (@"(if (equal vl-dir \\"input\\") \\"\\" (concat vl-width \\"'b0\\"))"),                       

Although if you're using systemverilog I would not use vl-width and instead use "'0".

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2015-01-12T15:03:37Z

Thanks a lot, I will try it when I come to office tomorrow, why I need this is RTL lint rule report bitwidth mismatch as error.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-12T15:51:43Z

IMO if a lint tool reports ".port('0)" as a width mismatch, that tool is broken. In contrast note ".port('h0)" is a mismatch.

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2015-01-13T09:40:23Z

above command works perfect.
could you help check why following command does not work ?

.si (@"(concat vl-width \"'b0\")"),
although I could use
.si ({@"vl-width"{1'b0}}),

regards
Arthas

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-13T12:49:52Z

vl-width is a number, and numbers do not automatically stringify in (Emacs-) Lisp.

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2015-01-14T02:04:33Z

si (@"(concat vl-width "'b0")"), can work, but I am confused about when to use \" and when to use ", could you help clarify it?

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-15T00:25:03Z

" is part of the template,
" passes a backslash quote to emacs expression
\" passes a quote to emacs expression.

Generally \" is what you want.

Original Redmine Comment
Author Name: kishore babu nainappagari
Original Date: 2017-01-13T20:07:26Z

Hi,

I am encountering an error with the following auto_template. I am trying to make output's floating and input's tied to zero's.

May I pls know if I am missing anything here.

in rtl:

input [`LP_CMD_WIDTH-1:0] lp_cmd_type;

output lp_ack;

info that's placed in Testbench top AUTO_TEMPLATE

     .lp_cmd_\(.*\)      (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),

connection gets expanded as below:

  .lp_ext_ack   (),
  .lp_cmd_type	((1+(`LP_CMD_WIDTH-1))'b0), // Templated   // error seen at this line

Error msg seen:

ncvlog: *E,EXPRPA (abc_wrap.sv,391|48): expecting a right parenthesis (')') [12.3.4(IEEE)].

Pls suggest

rgds
Kishore

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2017-01-13T22:59:44Z

!!

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2017-01-13T23:00:42Z

please check attached file "input0-floating.jpg"

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-01-13T23:58:35Z

Ignore verilog-mode this is really just a Verilog question. "(1+(LP_CMD_WIDTH-1))'b0" isn't legal verilog. The way you write this is just "'0" in SystemVerilog, or if you're stuck in old-school Verilog "{(1+(LP_CMD_WIDTH-1)){1'b0}}". Then morph that into the auto template.

Original Redmine Comment
Author Name: kishore babu nainappagari
Original Date: 2017-01-14T00:50:10Z

Thanks for the suggestions Wilson and Jie Xiao

rgds
Kishore

Original Redmine Comment
Author Name: Jie Xiao
Original Date: 2018-04-18T21:44:24Z

why sometimes I need to modify it as

.comp_1_db (@"(if (string= vl-dir "input" ) (concat vl-width "'b0" ) "" )" ), //default input 0"
.comp_1_db (@"(if (string= vl-dir \"input\" ) (concat vl-width \"'b0\" ) \"\" )" ), //default input 0", if write like this, it will have syntax issue.

also find another case, 723 line need use ", 724 can pass with \"

723 .DEBUG_BUS_o (@"(if (= @ 0) "yuv444_down_DEBUG_BUS" "yuv444_down_1_DEBUG_BUS" )" ),
724 .INT_(.).*o (@"(if (= @ 0) \"YUV444_DOWN_INT\1_INT\" \"YUV444_DOWN@_INT\1_INT\")" ),

Really confused with " and \"

could you help answer, thank you very much .

Original Redmine Comment
Author Name: Engr vns
Original Date: 2019-02-07T19:03:10Z

Here's an example that works without issues
.lp_cmd.* (@"(if (equal vl-dir \"output\") \"\" \"'0\")"),

If the port matching the port name regex does not exist on the instance then the expansion will get messed up.
You need to make sure that the port does indeed exist.

-VS

Jie Xiao wrote:

I want to tie all input of a bus to 0 and all output floating as

[...]
but it does not work, could you help on this.

Thanks a lot.
Arthas Jie Xiao

Original Redmine Comment
Author Name: Stefan Sredojevic
Original Date: 2019-05-08T13:30:47Z

This one worked for me, I had a problem with solutions above because I had parametrized ports thus output was like:

.some_port (SOME_PARAMETER'b0)
</code>

Solution to this problem, one more do concat:

.\(axi_ar.+\)  (@"(if (equal vl-dir \\"output\\") \\"\\" (concat \\"{\\" (concat vl-width \\"{1'b0}}\\")))"), //Leave read ports unconnected or fixed to 0
.\(axi_r.+\)   (@"(if (equal vl-dir \\"output\\") \\"\\" (concat \\"{\\" (concat vl-width \\"{1'b0}}\\")))"), //Leave read ports unconnected or fixed to 0
</code>