Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

In 3.868, unable to $sscanf a string (system verilog) #866

Closed
veripoolbot opened this issue Dec 24, 2014 · 2 comments
Closed

In 3.868, unable to $sscanf a string (system verilog) #866

veripoolbot opened this issue Dec 24, 2014 · 2 comments
Assignees
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

Comments

@veripoolbot
Copy link
Contributor


Author Name: David Pierce
Original Redmine Issue: 866 from https://www.veripool.org
Original Date: 2014-12-24
Original Assignee: Wilson Snyder (@wsnyder)


I have a DPI-C function that returns a string,

import "DPI-C" context function string getRPIPE(
   input int fd, input int blocking
); 

and a string variable,

string ipcstring;

assigned to the string returned by the function,

ipcstring = getRPIPE(rxfile, 0);

When I try this

if( $sscanf(ipcstring, "write %d %d", addrval, dataval) == 2 ) begin   // addrval and dataval are integers

I get this

In file included from Vclient__ALLcls.cpp:3:
./Vclient.cpp:237:18: error: no matching function for call to 'VL_SSCANF_IQX'
                     if ((2U == VL_SSCANF_IQX(64,vlTOPp->v__DOT__b0__DOT__ipcstring,"writ...
                                ^~~~~~~~~~~~~
/usr/local/share/verilator/include/verilated.h:375:14: note: candidate function not viable: no
       known conversion from 'string' (aka 'basic_string<char, char_traits<char>, allocator<char>
       >') to 'QData' (aka 'unsigned long') for 2nd argument
extern IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...);
              ^

Here's the verilator command line:

verilator --cc --exe --trace \
           --compiler gcc \
           -Wno-WIDTH -sv \
           -I/opt/tools/verilator-3.868/include/vltstd \
           client.sv \
           mybus_bfm.sv \
           dapfuncs.o sc_main.cpp -LDFLAGS -lc

As a point of reference, the code works as is in both modelsim and ncsim

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-12-25T02:51:59Z


Pushed to git towards 3.869.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-13T01:40:52Z


In 3.870.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
Projects
None yet
Development

No branches or pull requests

2 participants