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Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 878 from https://www.veripool.org
Original Date: 2015-02-03
Original Assignee: Iztok Jeras (@jeras)
Hi,
ModelSim is the only freely available big 3 simulator (with limitations) with comprehensive support of SystemVerilog RTL features.
The limitations of the Altera ModelSim Starter Edition are to 10000 lines of source code, and some object oriented features are missing, previously objects were not allowed, not they will compile, but constrained randomization would complain about licensing. Still as far as I know all RTL SystemVerilog features are available.
I would like to use it to prepare test units for bug reports.
Regards,
Iztok Jeras
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-03T20:17:39Z
No argument that ModelSim would be useful. If you would like it, can you please provide a patch to test_regress/driver.pl to support it? It should be pretty obvious how to modify it - search for vcs and copy appropriately. After you run all the tests no doubt some other cleanup will be required too, but shouldn't be too bad. Thanks
Original Redmine Comment
Author Name: Iztok Jeras (@jeras)
Original Date: 2015-02-03T23:33:52Z
Hi,
I attached a version of test_regress/driver.pl which kind of works with ModelSim. I would have done this earlier, but I never wrote any code in perl.
Known issues:
ModelSim stores all compiled objects in a "work" library, which is created using the command 'vlib work'. I attempted to create a separate work library for each test, I am not sure I have done it right.
The execute command 'vsim' requires the name of the top level module, it seems this is 'top' for all tests, but I might be wrong.
Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 878 from https://www.veripool.org
Original Date: 2015-02-03
Original Assignee: Iztok Jeras (@jeras)
Hi,
ModelSim is the only freely available big 3 simulator (with limitations) with comprehensive support of SystemVerilog RTL features.
The limitations of the Altera ModelSim Starter Edition are to 10000 lines of source code, and some object oriented features are missing, previously objects were not allowed, not they will compile, but constrained randomization would complain about licensing. Still as far as I know all RTL SystemVerilog features are available.
I would like to use it to prepare test units for bug reports.
Regards,
Iztok Jeras
The text was updated successfully, but these errors were encountered: