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Support arrayed interfaces #879
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Original Redmine Comment If you are willing to have constant indices this should be doable, that is "iface[1].foo = bar", not "iface[signal].foo = bar". It would be excellent if you are willing to attack this: FYI interfaces become both a module-like reference and a variable referencing that cell's variable. The module reference needs to be expanded into one for each array instance - see how V3Cell does this. Then the variables likewise need to be expanded into references into each instance.
Feel free to ask questions. |
Original Redmine Comment Patch available: phb/verilator-dev@e5de9c8 It's not ready to be pulled yet -- fair bit of cleanup needed, but as far as I can tell at the moment, it seems to work -- any high-level feedback appreciated (I know there is lots of cleanup to be done). |
Original Redmine Comment Feedback from Wilson that ended up on a different ticket:
I'm going to keep holding off on this one until we get some other issues out of the way (994, 997, 996) -- I am seeing issues that I think stems from this patch when running large designs with heavy use of arrayed interfaces, but I haven't been able to isolate into a testcase yet. |
Original Redmine Comment https://github.com/phb/verilator-dev/tree/arrayed_interfaces_879 Rebased on top of master and addressed comments. I fixed one issue that previously would cause parameterized arrayed interfaces to fail. |
Original Redmine Comment Found some more issues with this patch in bigger designs. Will keep working on it. |
Original Redmine Comment https://github.com/phb/verilator-dev/tree/issue879
I'm feeling pretty confident that this patch does what it set out to do. We're still a little ways from being able to run our main designs, but this should be good to pull and we'll follow up with additional patches as we go along. |
Original Redmine Comment This branch was provided which also fixes #�. https://github.com/toddstrader/verilator-dev/commits/issue1001.3 This is fixed in git towards 3.880. Thanks to Todd Strader et al for this patch, I made some style changes and added a common function to find arrays to reduce some code duplication. |
Original Redmine Comment In 3.880. |
Author Name: Varun Koyyalagunta
Original Redmine Issue: 879 from https://www.veripool.org
Original Date: 2015-02-06
Apologies if this is a duplicate.
Instantiating arrays of SystemVerilog interfaces would be a useful feature for my work. Is there any work being done on this? I am willing to work on it if it is tractable and someone can give me some pointers.
An example -
Currently errors with -
It also seems that supporting arrayed interfaces inside a generate block is a separate issue ([[#�]]), but I can live without that feature for now.
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