Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-13T18:15:12Z

From the docs:

"Abstract Syntax Tree

Verilog::Parser knows enough to make a complete Abstract Syntax Tree (AST) of Verilog syntax, however this hasn't been implemented yet. This would allow any arbitrary transformation of Verilog syntax (everthing is known excluding whitespace). If you'd find this useful please contact the author."

It's not obvious what the format should be. You'll need to say what you're interested in.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-06-16T19:25:51Z

Closing for now, if you want to debate what this should look at start a discussion on the forums and we'll hash something out.