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sign extension is not working properly when signed value is assigned to unsigned structure element #882

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veripoolbot opened this issue Feb 9, 2015 · 4 comments
Closed

sign extension is not working properly when signed value is assigned to unsigned structure element #882

veripoolbot opened this issue Feb 9, 2015 · 4 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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Author Name: Iztok Jeras (@jeras)
Original Redmine Issue: 882 from https://www.veripool.org
Original Date: 2015-02-09
Original Assignee: Wilson Snyder (@wsnyder)

Hi,

Sign extension is not working properly when signed value is assigned to unsigned structure element. While it is working properly if the destination is a normal unsigned variable.

A regression test is attached, I did not know which of the existing tests would be appropriate, so I created a new file. The test is passing if run using ModelSim using the edited driver.pl from Issue #878.

$ t/t_math_signed6.pl -ms
======================================================================
Use of uninitialized value $ENV{"VERILATOR_ROOT"} in concatenation (.) or string at ./driver.pl line 327.
ms/t_math_signed6: ==================================================
ms/t_math_signed6: Compile
	vlib obj_dir/ms_t_math_signed6/work &&  vlog -sv -work obj_dir/ms_t_math_signed6/work  -f input.vc t/t_math_signed6.v obj_dir/ms_t_math_signed6/Vt_math_signed6__top.v   > obj_dir/ms_t_math_signed6/ms_compile.log
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
Start time: 12:45:54 on Feb 09,2015
vlog -sv -work obj_dir/ms_t_math_signed6/work -f input.vc t/t_math_signed6.v obj_dir/ms_t_math_signed6/Vt_math_signed6__top.v 
-- Compiling module t
-- Compiling module top

Top level modules:
	top
End time: 12:45:55 on Feb 09,2015, Elapsed time: 0:00:01
Errors: 0, Warnings: 0
ms/t_math_signed6: Run
	echo q | vsim -lib obj_dir/ms_t_math_signed6/work -c -do 'run -all;quit'  top   > obj_dir/ms_t_math_signed6/ms_sim.log
Reading pref.tcl

1. 10.3c

1. vsim -lib obj_dir/ms_t_math_signed6/work -c -do "run -all;quit" top 
1. Start time: 12:45:59 on Feb 09,2015
1. Loading sv_std.std
1. Loading obj_dir/ms_t_math_signed6/work.top
1. Loading obj_dir/ms_t_math_signed6/work.t
1. run -all
1. *-* All Finished *-*
1. ** Note: $finish    : t/t_math_signed6.v(28)
1.    Time: 0 ps  Iteration: 0  Instance: /top/t
1. End time: 12:46:02 on Feb 09,2015, Elapsed time: 0:00:03
1. Errors: 0, Warnings: 0
ms/t_math_signed6: Test PASSED
Use of uninitialized value $ENV{"VERILATOR_ROOT"} in concatenation (.) or string at ./driver.pl line 327.
==SUMMARY: Left NO-FORKER  Passed 1  Unsup 0  Skipped 0  Failed 0

======================================================================
TESTS Passed 1  Unsup 0  Skipped 0  Failed 0  Time 0:11
TESTS Passed 1  Unsup 0  Skipped 0  Failed 0  Time 0:11

Regards,
Iztok Jeras
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-12T00:48:58Z

Thanks for the test, I added your test to git. However, it passes for me against verilator trunk, and also against VCS. If you can get it to disagree between verilator & vcs I'll take a look.

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Original Redmine Comment
Author Name: Iztok Jeras (@jeras)
Original Date: 2015-02-12T09:12:09Z

Hi Wilson,

It seems the testcase does PASS in verilator despite an error, and I am not sure you noticed it:

%Error: t/t_math_signed6.v:27:  got='h00f5 exp='hfff5
*-* All Finished *-*

This is because a $stop is missing in the comparison function.

I asked a friend to run the simulation on ncsim, and I have tried "Riviera-PRO version 2014.10.81.5580" on http://www.edaplayground.com/ and there is no error reported, same as in ModelSim.

[2015-02-12 03:44:50 EST] vlib work && vlog '-timescale' '1ns/1ns' '-sv2k9' design.sv testbench.sv  && vsim -c -do "vsim +access+r; run -all; exit"  
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE "Pass 2. Processing instantiations."
MESSAGE "Pass 3. Processing behavioral statements."
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: t."
MESSAGE "$root top modules: t."
SUCCESS "Compile success 0 Errors 0 Warnings  Analysis time: 0[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
done
1. Aldec, Inc. Riviera-PRO version 2014.10.81.5580 built for Linux64 on October 24, 2014.
1. HDL, SystemC, and Assertions simulator, debugger, and design environment.
1. (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim +access+r;
1. ELBREAD: Elaboration process.
1. ELBREAD: Elaboration time 0.0 [s].
1. KERNEL: Main thread initiated.
1. KERNEL: Kernel process initialization phase.
1. KERNEL: Time resolution set to 1ns.
1. ELAB2: Elaboration final pass...
1. ELAB2: Create instances ...
1. ELAB2: Create instances complete.
1. SLP: Started
1. SLP: Elaboration phase ...
1. SLP: Elaboration phase ... done : 0.1 [s]
1. SLP: Generation phase ...
1. SLP: Generation phase ... done : 0.1 [s]
1. SLP: Finished : 0.2 [s]
1. SLP: 0 primitives and 1 (100.00%) other processes in SLP
1. SLP: 2 (100.00%) signals in SLP and 0 interface signals
1. ELAB2: Elaboration final pass complete - time: 0.2 [s].
1. KERNEL: SLP loading done - time: 0.0 [s].
1. KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
1. KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com.
1. KERNEL: SLP simulation initialization done - time: 0.0 [s].
1. KERNEL: Kernel process initialization done.
1. Allocation: Simulator allocated 5278 kB (elbread=1023 elab2=4104 kernel=149 sdf=0)
1. KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
1. KERNEL: *-* All Finished *-*
1. RUNTIME: Info: RUNTIME_0068 testbench.sv (31): $finish called.
1. KERNEL: Time: 0 ns,  Iteration: 0,  Instance: /t,  Process: @INITIAL#19_0@.
1. KERNEL: stopped at time: 0 ns
1. VSIM: Simulation has finished. There are no more test vectors to simulate.
exit
1. VSIM: Simulation has finished.
Done

Regards,
Iztok Jeras

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-12T12:49:32Z

Fifty places to copy the correct macro from, and I picked the one exception!

Anyhow fixed in git towards 3.869.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-02-13T01:41:53Z

In 3.870.

@veripoolbot veripoolbot added area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed labels Dec 22, 2019
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