Author Name: David Poole
Original Redmine Issue: 886 from https://www.veripool.org
Original Date: 2015-02-25
Original Assignee: Wilson Snyder (@wsnyder)

Verilator 3.871 devel rev verilator_3_866-58-ga89502b
(Also originally tested with release verilator before fetching git tip.)

When I use the --pins-bv 8 to convert a 10-bit signal to a sc_bv array, the resulting C++ code fails to compile. I have a small test case.

Tested under both recent Linux (gcc) and recent OSX (clang).

Example error:
Vctwin.cpp:90:5: error: invalid cast from type ‘sc_core::sc_in<sc_dt::sc_bv<10> >’ to type ‘IData {aka unsigned int}’

Generated code:
85 VL_INLINE_OPT void Vctwin::_combo__TOP__1(Vctwin__Syms* __restrict vlSymsp) {
86 VL_DEBUG_IF(VL_PRINTF(" Vctwin::_combo__TOP__1\n"); );
87 Vctwin* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
88 // Body
89 vlTOPp->__Vcellinp__v__ch_in[5U] = (IData)(vlTOPp->ch_in)
90 [5U];
91 vlTOPp->__Vcellinp__v__ch_in[4U] = (IData)(vlTOPp->ch_in)
92 [4U];
93 vlTOPp->__Vcellinp__v__ch_in[3U] = (IData)(vlTOPp->ch_in)
94 [3U];
95 vlTOPp->__Vcellinp__v__ch_in[2U] = (IData)(vlTOPp->ch_in)
96 [2U];
97 vlTOPp->__Vcellinp__v__ch_in[1U] = (IData)(vlTOPp->ch_in)
98 [1U];
99 vlTOPp->__Vcellinp__v__ch_in[0U] = (IData)(vlTOPp->ch_in)
100 [0U];
101 }

If I don't use --pins-bv, the ch_in array is an array of uint32_t. However, my verification simulation is failing (incorrect values) so I'm trying the more accurate (but slower) single bit signals to see if that helps.