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Author Name: Sean de la Haye (@seandlh)
Original Redmine Issue: 9 from https://www.veripool.org
Original Date: 2008-05-21
Original Assignee: Wilson Snyder (@wsnyder)
This code is not parsed correctly...
module assertion_error;
wire clk;
wire rst_n;
reg a;
reg b;
sample_assertion: assert property (
@(posedge clk)
disable iff (!rst_n)
(a !== b)
);
endmodule
I receive this error:
%Error: assertion_error.sv:6: syntax error, unexpected ':', expecting '('
Exiting due to errors
I'm using version 3.035 of Verilog-Perl on a RedHat Opteron machine.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-06-04T16:36:40Z
This isn't proving easy, because there are other SystemVerilog assertion parse issues that haven't been added yet. It will take a while to get all of this in and working; if you'd like to help out drop me a line.
Author Name: Sean de la Haye (@seandlh)
Original Redmine Issue: 9 from https://www.veripool.org
Original Date: 2008-05-21
Original Assignee: Wilson Snyder (@wsnyder)
The text was updated successfully, but these errors were encountered: