verilog-mode: Indenting user defined declarations
First of all, thank you for this awesome mode which I cannot do without for all my design/verification activity.
We rely on user defined structs a lot in our RTL and I can't seem to find (maybe it does't exist?) the right hooks in the verilog-mode for allowing the customization I am looking for. When we have a user defined type, like a struct which is typedefed, in the declarations, there seems to be no control on how much indent is to be applied to the type vs the variable name. What I am trying to propose is to provide a hook to the user for userdefined types to allow customization as shown below.This is what I am talking about:
Code before indentation: output wire abc; output my_stuct_t s_var; output wire xyz; Code after indentation: output wire abc; output my_stuct_t s_var; output wire xyz; Code after proposed indentation hook: output wire abc; output my_stuct_t s_var; output wire xyz;
I have made an attempt at doing this with the verilog-mode version 2015-03-13-7ee11f6-vpo and have attached the verilog-mode.el here. I have run a few experiments on it and it seems to do what I am looking for.
I have added a hook called verilog-indent-declaration-userdef, which when set, indents the structs and the surrounding declarations as shown in the example above. If it is nil, it keeps the same behavior as before. To support this, I added a few regex's, viz verilog-declaration-re-2-userdef, verilog-declaration-re-1-userdef, verilog-declaration-re-userdef and verilog-declaration-re-no-userdef. The functions I have added are: verilog-forward-userdef-declaration and verilog-backward-userdef-declaration.
Obviously, I don't have a test suite, that you probably have, to validate if I have broken anything else.
Please consider adding this feature to the verilog-mode.el so that I may be able to take advantage the updates in the future.
Thanks for taking the time to read this.
#1 Updated by Alex Reed almost 5 years ago
Thanks for the suggestion and proposed code. To make it easier to review/test and iterate on your patch, would you please fork the github repository (https://github.com/veripool/verilog-mode) and update this issue with the location of your feature branch? Once you've cloned the git repo, you can also run 'make && make test' to see if you've broken anything.
#4 Updated by Alex Reed almost 5 years ago
- Assignee changed from Michael McNamara to Ravi Karanam
Thanks for the patch! I pulled your changes and rebased them onto veripool/verilog-mode's current master. I also fixed some compile warnings and temporarily enabled verilog-indent-declaration-userdef. These can be found at https://github.com/acr4/verilog-mode/tree/issue-904.
When running the test suite with this new feature enabled, some existing tests break. autoinoutmodport_borduas_type.v properly indents the user type, but puts a space in the middle of the 'input' keyword on the last module port. autooutput_comma.v aborts with an "Invalid search bound (wrong side of point)" message which needs to be investigated further.
Can you pull my modifications and continue tweaking? I'll also take a look if I have some bandwidth later this week.
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