New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
verilog-mode: Indenting user defined declarations #904
Comments
Original Redmine Comment Hi Ravi, Thanks for the suggestion and proposed code. To make it easier to review/test and iterate on your patch, would you please fork the github repository (https://github.com/veripool/verilog-mode) and update this issue with the location of your feature branch? Once you've cloned the git repo, you can also run 'make && make test' to see if you've broken anything. Thanks, -Alex |
Original Redmine Comment See also #�. I think this should use verilog-typedef-regexp. |
Original Redmine Comment I have forked here: https://github.com/ravikirankm/verilog-mode. All the tests passed with my updates. |
Original Redmine Comment Hi Ravi, |
Original Redmine Comment Still present. |
Original Redmine Comment Closing due to age, appears abandoned. Open new bug if otherwise please. |
Author Name: Ravi Karanam
Original Redmine Issue: 904 from https://www.veripool.org
Original Assignee: Ravi Karanam
Hi,
First of all, thank you for this awesome mode which I cannot do without for all my design/verification activity.
We rely on user defined structs a lot in our RTL and I can't seem to find (maybe it does't exist?) the right hooks in the verilog-mode for allowing the customization I am looking for. When we have a user defined type, like a struct which is typedefed, in the declarations, there seems to be no control on how much indent is to be applied to the type vs the variable name. What I am trying to propose is to provide a hook to the user for userdefined types to allow customization as shown below.
This is what I am talking about:
I have made an attempt at doing this with the verilog-mode version 2015-03-13-7ee11f6-vpo and have attached the verilog-mode.el here. I have run a few experiments on it and it seems to do what I am looking for.
I have added a hook called verilog-indent-declaration-userdef, which when set, indents the structs and the surrounding declarations as shown in the example above. If it is nil, it keeps the same behavior as before. To support this, I added a few regex's, viz verilog-declaration-re-2-userdef, verilog-declaration-re-1-userdef, verilog-declaration-re-userdef and verilog-declaration-re-no-userdef. The functions I have added are: verilog-forward-userdef-declaration and verilog-backward-userdef-declaration.
Obviously, I don't have a test suite, that you probably have, to validate if I have broken anything else.
Please consider adding this feature to the verilog-mode.el so that I may be able to take advantage the updates in the future.
Thanks for taking the time to read this.
Sincerely,
Ravi
The text was updated successfully, but these errors were encountered: