Original Redmine Comment
Author Name: Alex Reed
Original Date: 2015-03-27T15:11:47Z

Thanks for the report. I'm going to assume you're using the latest released version (2015-03-13-7ee11f6-vpo) or possibly even the latest revision posted on github (951f48b).


This regression was partially introduced in d05c01d. This affects subsequent named assertions after "@Property p ... endproperty: p@" (i.e. if you have 2+ named assertions immediately after a labeled endproperty, then the first assertion is indented correctly but the rest are not.). Interestingly, if the first assertion is not labeled, then subsequent assertions (labeled or not) are also indented incorrectly. This appears to have existed for quite some time (possibly always?). If you remove the "@: p@" from the "@endproperty@", things seem to be okay.



Root cause is related to the parser seeing "@endproperty : p@" and thinking it looks like "@:@".



I have updated an existing test-case and patched verilog-mode.el. You may grab the latest version from https://github.com/veripool/verilog-mode or wait for a new release on http://www.veripool.org/projects/verilog-mode/wiki/Installing.