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warning in signals with width between 32 and 64 bits #912

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veripoolbot opened this issue Apr 24, 2015 · 2 comments
Closed

warning in signals with width between 32 and 64 bits #912

veripoolbot opened this issue Apr 24, 2015 · 2 comments
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed

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Author Name: Alfonso Martínez
Original Redmine Issue: 912 from https://www.veripool.org
Original Date: 2015-04-24
Original Assignee: Wilson Snyder (@wsnyder)

Hi!

I am having some "large integer implicitly truncated to unsigned type" warning when running make on a file produced with verilator. The warning is produced with signals between 32 and 64 bits wide.

I attach a file reproducing the problem, and the command I am running is:

verilator --sc --pins-bv 2 bug_large_integer_warning.sv && cd obj_dir && make -Bf Vbug_large_integer_warning.mk && cd ..

Thank you and good day!
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-04-29T01:32:44Z

Thanks for the testcase, obviously the warning was harmless in this case.

Fixed in git towards 3.873.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-06T18:03:58Z

In 3.874.

@veripoolbot veripoolbot added area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed labels Dec 22, 2019
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: fixed Closed; fixed
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