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Verilog::Parser can't handle "`\" token in macro definition #915

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veripoolbot opened this issue May 3, 2015 · 3 comments
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Verilog::Parser can't handle "`\" token in macro definition #915

veripoolbot opened this issue May 3, 2015 · 3 comments
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Author Name: Anton Rapp
Original Redmine Issue: 915 from https://www.veripool.org
Original Date: 2015-05-03
Original Assignee: Wilson Snyder (@wsnyder)

On:

define ABC(a,b,c) \ $display(a,"bc\n`")

`ABC("a",b,c)

Parser fails with
%Error: T.v:9: " not terminated at EOF When "\n" character is replaced by "n" the error doesn't appear. "\n" doesn't work either.
According to http://www.eda.org/sv/SystemVerilog_3.1a.pdf document (page 343) `\ is acceptable.
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-05-08T01:44:48Z

Fixed in git towards 3.413. This is a IEEE spec hole, as \n' is actually an legal identifier name in other contexts, but I'll do what other simulators do.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-06T18:04:39Z

In Verilator 3.874.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-26T10:30:40Z

In 3.414.

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