Author Name: Patrick Maupin (@pmaupin)
Original Redmine Issue: 918 from https://www.veripool.org
Original Date: 2015-05-13
Original Assignee: Wilson Snyder (@wsnyder)

module dummy1(o);
     output [31:0] o;
     assign o = 32'h12345678;
endmodule

module dummy2(o);
     output [31:0] o;

     dummy1 dummy(x);
     assign o = x;

endmodule

In this code, x is correctly flagged as an implicit wire, but the width of x appears to be propagated up from dummy1, such that the output o of dummy2 is 32h'12345678.

SO, if I just take a pile of code that I'm handed and verilate it as-is, without bothering with the warnings, I get different results than other simulators...

This was tested with 3.872.

Thanks for an awesome piece of software!