Author Name: Dan Moore
Original Redmine Issue: 92 from https://www.veripool.org
Original Date: 2009-05-26
Original Assignee: Wilson Snyder (@wsnyder)

Hello, thanks for a great project.

I'm getting errors out of vppreproc when it encounters the System Verilog typedef statements. e.g.:

%Error: /tmp/tbox.vs:2: syntax error, unexpected "bit"
%Error: /tmp/tbox.vs:2: Signal declaration outside of module definition
%Error: /tmp/tbox.vs:3: syntax error, unexpected "IDENTIFIER"

`default_nettype none
typedef bit node;
typedef node node_t;

I was able to work around the issue, but does vppreproc support this? Thanks.