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SystemVerilog class auto declaration line up #920
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Original Redmine Comment Dang - bad synopsis. Should be "auto variable line up". Have another request for declarations... |
Original Redmine Comment Here's a suggestion from Greg Waters: Hi Alex, More generally, how about adding a special comment marker? If a line within a declaration or port “region” would be auto-indented, but it has an end-of-line comment with the special mark, can the autoindenter leave that line alone and just auto-indent the other lines (which don’t have a user typedef in them)? Suppose the “keep-indent” marker is “//.”. We could improve user-type indentation this way (I use dot-space here to suppress auto-replace in e-mail composer):
With the help of this marker, Verilog-mode can continue to re-indent the unmarked lines nicely. The marked lines would have manual indentation. Thanks --Greg |
Original Redmine Comment Dang again. Please ignore the previous update. It belongs with item 923. |
Original Redmine Comment Hi Monte, |
Original Redmine Comment FWIW I added ``` for him, as I can edit comments (pencil icon which only appears to moderator or original contributor). |
Original Redmine Comment Still present, perhaps someone would like to contribute a patch? |
Author Name: Monte Becker
Original Redmine Issue: 920 from https://www.veripool.org
Hi there:
When creating a function or task in a class, I like to line up my declarations. For example:
Notice how the variables a, b and c are aligned. Is there Verilog-Mode support for this?
Thanks, Monte
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