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SystemVerilog class auto declaration line up #920

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veripoolbot opened this issue May 15, 2015 · 6 comments
Open

SystemVerilog class auto declaration line up #920

veripoolbot opened this issue May 15, 2015 · 6 comments
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Author Name: Monte Becker
Original Redmine Issue: 920 from https://www.veripool.org


Hi there:

When creating a function or task in a class, I like to line up my declarations. For example:

bit        a;
bit [95:0] b;
foo_type   c;  // foo_type is user defined

Notice how the variables a, b and c are aligned. Is there Verilog-Mode support for this?

Thanks, Monte

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Original Redmine Comment
Author Name: Monte Becker
Original Date: 2015-05-15T13:11:50Z


Dang - bad synopsis. Should be "auto variable line up". Have another request for declarations...

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Original Redmine Comment
Author Name: Monte Becker
Original Date: 2015-05-15T13:19:32Z


Here's a suggestion from Greg Waters:

Hi Alex,
I add the “var” keyword in front of user types in a declaration statement or ANSI port item, to give the parser more clues that a user typedef name precedes the port or variable name. I mention that in case you can build on it to improve indentation for types.

More generally, how about adding a special comment marker? If a line within a declaration or port “region” would be auto-indented, but it has an end-of-line comment with the special mark, can the autoindenter leave that line alone and just auto-indent the other lines (which don’t have a user typedef in them)?
This give the user a way to auto-indent declarations and ANSI ports that have built-in type names, while not affecting the ones that Verilog-mode can’t comprehend.

Suppose the “keep-indent” marker is “//.”. We could improve user-type indentation this way (I use dot-space here to suppress auto-replace in e-mail composer):

module foo
.(input logic. . . . . . . . . . .clk,
..input my_pkg::user_type. . . . .keep_type_way_left, //.  <==Keep-indent marker
..output logic . . . . . . . . . .done);

import my_pkg::*;
logic [7:0]. . . . . . . . .city_bus;
var user_type. . . . . . . .keep_type_also_way_left; //.  <==Keep-indent marker

endmodule

With the help of this marker, Verilog-mode can continue to re-indent the unmarked lines nicely. The marked lines would have manual indentation.

Thanks --Greg

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Original Redmine Comment
Author Name: Monte Becker
Original Date: 2015-05-15T13:20:58Z


Dang again. Please ignore the previous update. It belongs with item 923.

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Original Redmine Comment
Author Name: Alex Reed
Original Date: 2015-05-15T13:47:25Z


Hi Monte,
Can you try adding the formatted text again, but use the < pre > and < /pre > decorators (without the spaces) to keep your desired formatting intact?

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-05-15T13:54:21Z


FWIW I added ``` for him, as I can edit comments (pencil icon which only appears to moderator or original contributor).

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:22:04Z


Still present, perhaps someone would like to contribute a patch?

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