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SystemVerilog class auto formal declaration line up #921

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veripoolbot opened this issue May 15, 2015 · 2 comments
Closed

SystemVerilog class auto formal declaration line up #921

veripoolbot opened this issue May 15, 2015 · 2 comments
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Author Name: Monte Becker
Original Redmine Issue: 921 from https://www.veripool.org

Hi there:

I like to indent my class function and task formal declaration consistently like this:

task do_good_work ( bit        variable1,
                     bit [19:0] variable2,
                     footype    variable3 );

Notice that variable* are stacked. Is there support in VerilogMode for that? Thanks in advance,

Monte
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-05-15T13:55:01Z

Added pre's.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:25:11Z

This should fall out if #� is fixed.

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