Author Name: Jonathon Donaldson
Original Redmine Issue: 930 from https://www.veripool.org
Original Date: 2015-06-09

Verilator doesn't seem to like files with a .c extension. If my C source files end in .cpp things work just fine but if it has a .c extension I get a weird error. According to the error message it almost seems like verilator is trying to parse the file as a verilog file instead of a C file. The documentation states that verilator supports file extensions of [.cpp/.c/.cc/...etc...]. The error message I get is:

%Error: t_dotc_file.c:8: syntax error, unexpected '#'
%Error: t_dotc_file.c:8: Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: include
%Error: t_dotc_file.c:9: Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: include
%Error: t_dotc_file.c:17: Unsupported: SystemVerilog 2005 reserved word not implemented: new
%Error: Exiting due to 4 error(s)

I have attached an example in test_regress format.

Is there some other switch I need to enable to get this to work? If I simply change the extension of the .c file to .cpp then all is well. That doesn't seem right...

I verilate like so:

verilator_bin \
  -cc \
  --top-module t_dotc_file \
  t_dotc_file.v \
  --exe \
  t_dotc_file.c