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tracing configuration does not work #932
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Original Redmine Comment I have discovered that to have a module with working tracing, the module "above" it must have its trace on. That would explain why the tracing of primitives works as expected since they are always the leaves in the hierarchy tree. Best regards, Frederic Requin |
Original Redmine Comment Hello, here are my changes in case you want to experiment with them. the "tracing_on" is a little bit hacky :-) Regards, Frederic Requin |
Original Redmine Comment It seems like you figured it out. Is there any change you're still advocating? (I fixed the docs to make a note about cells under the tracing_off command; it had been only under the pragma.) |
Original Redmine Comment I like the tracing_on feature in the verilator_config. |
Original Redmine Comment Finally got around to the tracing_on improvement, added coverage_on and lint_on also. Fixed in git towards 3.875. |
Original Redmine Comment In 3.876. |
Author Name: Frederic Requin
Original Redmine Issue: 932 from https://www.veripool.org
Original Date: 2015-06-18
Hello,
before I was using /* verilator tracing_on/off */ around my modules to activate/deactivate tracing.
Starting with verilator v3.866, this stopped working. Anyway, it was not a good solution because it introduced unwanted changes in the git repository.
So, I tried some experiments with `verilator_config and tracing_off -file. It worked with some files but not with all of them.
Basically, the files found through search path can have the trace turned on or off, the files added to the project with `include cannot have their traces turned on or off.
The trace is globally on or off depending if the `verilator_config is located at the beginning or at the end of the testbench verilog file.
To summarize, the testbench file "tb_verilator.v" look like this:
The verilator command line is:
verilator tb_verilator.v -top-module tb_top -cc -O3 -trace -I./../../verilator/src/ -CFLAGS -Wno-attributes
(the folder "../../verilator/src/" contains the FPGA primitives in synthesisable verilog)
You would expect file6 and tb_top to be traced but in fact nothing is traced.
If I put the verilator_config block at the end of the file, everything but the FPGA primitives are traced.
I started investigating the issue.
What I noticed is that the search path is even added to the filenames found through `include, i.e. :
"../../verilator/src//../../ip_dir1/src/file1.v"
I fixed this problem by searching through the m_incDirFallbacks first (in V3Options::filepath)
This did not solve the tracing issue.
I activated debug output in preprocOpen(), V3PreProcImp::getStateToken() case ps_INCNAME:, addIgnore() and applyIgnores() to see how tracing property was applied to the files.
I also added a "tracing_on" keyword in the verilator_config block but I cannot make the tracing work reliably.
Best regards,
Frederic Requin
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