Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-06-22T17:02:32Z

Unfortunately this syntax requires an event simulator. While Verilator could ignore it, it would almost certainly just result in a mismatch with other simulators.

Original Redmine Comment
Author Name: John Demme (@teqdruid)
Original Date: 2016-11-15T18:26:23Z

Hi Wilson-

It be great if the parser supported this syntax and then errored out during elaboration of some other stage. This behavior is important for three use cases:

• The simulated design is pulling in a module which does not use this syntax, but is contained in a file with other modules which contain this syntax. This is common, especially for supporting simulation libraries from Altera.
• Verilator is being used for linting rather than simulation
• Verilator's parser is being pulled out and used for another purpose

I would really like to use Verilator for all three purposes.

~John

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2016-12-21T23:23:37Z

Parsing of && is now supported, but not arbitrary equations due to certain difficulties. This errors out later when the module is consumed (unless --bbox-unsup is used)

In git towards 3.891.

Original Redmine Comment
Author Name: John Demme (@teqdruid)
Original Date: 2016-12-22T00:08:14Z

Excellent! Thanks, Wilson.

I'll check it out in the next few days. Would be great if it not gets through that monster of an altera_mf.sv.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-01-15T17:18:33Z

In 3.900.