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Using ':' for end-lable instread of "// SysteVerilog #956
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Original Redmine Comment Some how my request got submitted before I finished filling it in; and I cannot edit :( Basically I, like an option to use the verilog-set-auto-endcomments use ':' for end-lables instead of "//". With a backward (or forward) compatable switch for users that what to strictly use IEEE 1364 syntax. |
Original Redmine Comment I like this idea (and I've even thought about implementing it before...) As you mention, this is only an IEEE 1800 syntax feature and is not backward compatible with IEEE 1364. If this were added to verilog-mode, I think it would require setting a variable (verilog-end-label-sv perhaps?) and only work if the specified buffer ends in an SV extension (verilog-sv-extensions = ). Assigning to myself and setting low priority. I'll get to it eventually... |
Original Redmine Comment From Kaushal Modi in www.veripool.org/issues/1038-Verilog-mode-Support-for-named-ends-Example-endclass-CLASSNAME-
Further review shows that the (unless ...) was added in 8f6e75d#diff-c480fc7ce25d2b23c9996dc931e5b3d9R2503 in 2004. I think it's safe to assume that this code needs to be re-evaluated. Please, hack away and see what you can come up with! :) |
Original Redmine Comment Cool! Any idea about that unless condition? |
Original Redmine Comment I missed reading these lines earlier when I posted that reply:
Alright, I'll look into the named end support. |
Original Redmine Comment Still missing feature AFAIK, perhaps someone would like to contribute a patch? |
If you want a truly lazy .emacs solution that you can hook on save (or run from shell since you've already succumbed to emacs for verilog-mode), I've been converting the // the : on save:
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Seems a good idea, pehaps you'd consider to conditionalize the code with a new variable and submit a pull request? |
I'd love to, but after some back and forth with my current employer, they won't let me work on open source anything. |
Author Name: Greg Hilton
Original Redmine Issue: 956 from https://www.veripool.org
Currently verilog-mode will place a end comment for functions, tasks, modules, primitives, classes, etc. Instead of "//" SystemVerilog's IEEE 1800 LRM suggests using ':'. It is not backward compatible with IEEE 1364, so maybe a
References from "IEEE Std 1800-2012":http://standards.ieee.org/getieee/1800/download/1800-2012.pdf
A.6.3 Parallel and sequential blocks
A.6.11 Clocking block
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