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Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2015-08-24T14:16:13Z
Have tested the same thing using VCS and it reports the same result as Verilator. Also the verilog standard says that the rigth side is extended to be the same width as the left side before the operation is done.
Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 959 from https://www.veripool.org
Original Date: 2015-08-19
For the following code
Verilator generates C++ code for the assignment as
where @vlTOPp->sig@ is a byte. So if @sig@ equals to @1'b1@, then @res@ will be @(0xffffU & ((0xFE) << 3U))@ instead of @(0xffffU & ((1'b0) << 3U))@.
Is this expected?
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