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incorrect simulation relating to operator NOT #959

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veripoolbot opened this issue Aug 19, 2015 · 2 comments
Closed

incorrect simulation relating to operator NOT #959

veripoolbot opened this issue Aug 19, 2015 · 2 comments
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resolution: no fix needed Closed; no fix required (not a bug)

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Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 959 from https://www.veripool.org
Original Date: 2015-08-19

For the following code

module test(sig, res);

input logic sig;
output [15:0] res;

assign res = (~sig << 3);

endmodule

Verilator generates C++ code for the assignment as

 vlTOPp->res = (0xffffU & ((~ (IData)(vlTOPp->sig)) << 3U));

where @vlTOPp->sig@ is a byte. So if @sig@ equals to @1'b1@, then @res@ will be @(0xffffU & ((0xFE) << 3U))@ instead of @(0xffffU & ((1'b0) << 3U))@.

Is this expected?
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-08-19T13:33:13Z

Can you please make this a self checking test in test_regress format? Assuming it passes on another simulator I'll take a look tonight, thanks.

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Original Redmine Comment
Author Name: Jie Xu (@jiexu)
Original Date: 2015-08-24T14:16:13Z

Have tested the same thing using VCS and it reports the same result as Verilator. Also the verilog standard says that the rigth side is extended to be the same width as the left side before the operation is done.

So the issue reported here is invalid.

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