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Restart alignment after empty or comments lines #960

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veripoolbot opened this issue Aug 19, 2015 · 1 comment · Fixed by #1800
Closed

Restart alignment after empty or comments lines #960

veripoolbot opened this issue Aug 19, 2015 · 1 comment · Fixed by #1800
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@veripoolbot
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Author Name: Enzo Chi
Original Redmine Issue: 960 from https://www.veripool.org

Currently the verilog-mode would try to align the signal name in the declaration with the port name as below:

     module img_cnt(
                    logic clk,
                    logic rst,
                    logic frame_vld,
                    logic line_vld,
                    logic data_vld
                    );
     
        // Expect to restart the alignment from here
        int unsigned      frame_cnt = 0;
        int unsigned      line_cnt = 0;
        int unsigned      data_cnt = 0;

But I think the declaration should has its own alignment (aligned '=' as bonus).

     module img_cnt(
                    logic clk,
                    logic rst,
                    logic frame_vld,
                    logic line_vld,
                    logic data_vld
                    );

        // Expect to restart the alignment from here
        int unsigned frame_cnt = 0;
        int unsigned line_cnt  = 0;
        int unsigned data_cnt  = 0;

So is it possible to add some variables to control restart the alignment after empty lines or comment lines?
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-11-19T13:27:53Z

Still a problem, perhaps someone would like to contribute a patch?

@gmlarumbe gmlarumbe mentioned this issue Aug 13, 2022
Merged
@gmlarumbe gmlarumbe linked a pull request Aug 13, 2022 that will close this issue
Tests: add testcases for issues 1272, 960, 955 and 585 #1800
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Tests: add testcases for issues 1272, 960, 955 and 585 gmlarumbe/verilog-mode
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