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AUTOARG order with AUTOINPUT #962
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Original Redmine Comment That version is 6 years old, there have been sorting fixes since then. Please try the latest version and if that fails send an example, thanks. |
Original Redmine Comment Hi, okay, tried the latest version and I've found the issue after experimenting. I was assuming the port numbering was generated from the I/O declarations but you use the port list. After re-running AUTO's I noticed the difference. So, the issue seems to come from the way autoargs generates the port list. I'm using both manually defined I/O declarations as well as AUTOINPUT and AUTOOUTPUT. The ordering of the port list changes for these which seems wrong. This is the ordering I get:
So there's a bug or feature in the AUTO's that swaps the ordering of ports. |
Original Redmine Comment Yes, that's a bug but not one that can be easily fixed because it must do the AUTOINPUTS first and cannot know relative position to insert them. To work around you'll need to put the AUTOARG before the other inputs. Sorry. Not that this isn't a bug, but of course code should not be written to ever use order based instantiation, and you should have your lint tool complain if someone does, but I assume you know that already. ;) |
Original Redmine Comment This isn't being used for instantiation, I'm using a script to pull out a number of signals and selecting the primary signal based on the declaration order. We have coding guidelines to allow us to more easily script stuff like this. Why does AUTOINPUT and AUTOOUTPUT reverse the order in the port list? Is that not just an array reverse? |
Original Redmine Comment AUTOINPUT is adding each insertion to the end of the list. That part should be easier to fix. |
Author Name: Shareef Jalloq
Original Redmine Issue: 962 from https://www.veripool.org
Original Date: 2015-09-04
Hi,
I'm running an older version of Verilog Perl, 3.223, so this might have been a bug that was fixed or my understanding is wrong.
I was assuming that ports_ordered would return a list of ports in the order they were defined in the modules. So the following port definitions:
would be returned as either {a,b,c,d} or {d,c,b,a} depending on the indexing you use. What I'm seeing is that some modules I get {d,c,a,b} returned.
I was using this functionality to pull out a list of signals and using the order to define signal 'a' as the primary and all others as secondary signals. But this doesn't seem to work.
Cheers.
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